The present invention relates generally to high density semiconductor memories which use a low voltage power supply, and, more particularly, to a high density semiconductor memory of this type having improved sense amplifier and refresh circuits.
In general, the continuing increases in the density of semiconductor memory devices have necessitated the use of commensurately lower power supply voltages therefor. More particularly, the increases in the density of semiconductor memory devices entails commensurate increases in the scale of integration of the circuit elements thereof. This ultimately results in smaller intervals between signal transmission lines, thinner gate oxide films for the MOS transistors, and, in general, a miniaturization of all of the circuit elements of the memory devices. The power supply voltage level used in such higher density semiconductor memory devices has to be decreased in order to prevent damage to these miniaturized circuit elements, and thus, to ensure reliability of operation of these memory devices. For example, a power supply voltage of 1.5V is currently being utilized in 64Mb DRAMs (dynamic random access memories).
The use of lower power supply voltages has led to the following problems. Namely, the use of lower power supply voltages has led to an increase in the soft error rates caused by alpha particles, and instabilities in the refresh voltage used to dynamically refresh the memory cells of a DRAM to compensate for charge which leaks from the memory cells during normal operation and used to restore the charge discharged from a memory cell after a read operation. Further, the use of lower power supply voltages has caused a commensurate reduction of the voltage difference between the power supply voltage and ground, thereby lowering the sensing margin of the sense amplifiers and consequently increasing the bit error rate for both read and write operations.
The above problems are particularly acute with respect to read or write operations regarding binary "1" data. Generally, binary "1" data is represented by a positive charge stored in the storage capacitor of a selected memory cell. During a read or refresh operation, this binary "1" data is read from the selected memory cell in the following manner. The charge stored on the storage capacitor of the selected memory cell is transferred through an access or select transistor of the memory cell to one of a pair of complementary bit lines, which is sometimes referred to as a charge sharing operation. A sense amplifier functions to amplify the resultant voltage difference between the complementary bit lines, in order to thereby establish the power supply voltage on one of the pair of bit lines and the ground voltage on the complementary one of the pair of bit lines. During a read operation, the data thus represented by the respective voltages on the complementary bit lines is then coupled to a corresponding pair of complementary data input/output (I/O) lines.
Before the end of the read or refresh cycle, the storage capacitor of the thusly discharged selected memory cell must be recharged, to thereby restore the read-out data. However, since the level of the restore voltage is limited to the low level of the power supply voltage, the quantity of charge which can be supplied to the storage capacitor of the selected memory cell is not sufficiently high to ensure adequate immunity from soft errors caused by alpha particles, thereby resulting in an undesirable data error rate.
One attempt at overcoming the above-described shortcomings of the presently available low-power, high-density semiconductor memory devices is embodied in a sense amplifier and peripheral circuit depicted in FIG. 1 and disclosed in U.S. Pat. No. 4,855,628, which is assigned to the assignee of the present application. With reference to FIG. 1, it can be seen that the sense amplifier includes an n-type latch consisting of NMOS transistors 20 and 21, and a p-type latch consisting of PMOS transistors 28 and 29. The peripheral circuit includes NMOS transistors 25, 26, and 27 which function to precharge and equalize the voltage of the bit lines BL and /BL to a reference voltage Vref, and NMOS transistors 31 and 32, which, in combination with NMOS capacitors 33 and 34, function to restore the charge on a selected memory cell 1 to a level of Vcc+alpha, in order to compensate for soft error, i.e., the loss of charge from the memory cell due to alpha particles.
The operation of the circuitry described above is discussed below with reference to both FIGS. 1 and 2, assuming that binary "1" data stored in the memory cell 1 is to be read therefrom (either during a refresh or memory access operation, such as a read operation).
When the semiconductor memory chip (not shown) containing the depicted circuitry becomes active, i.e., when the row address strobe signal (/RAS) goes to a logic "low" level, the word line WL1 is activated (i.e., raised to a logic "high" voltage level), thus turning on the select or access transistor 10 of the memory cell 1, which, in turn, allows the charge stored in the memory cell 1 to be transferred to the bit line BL. Thereafter, a control signal O1 is driven to a logic "high" level, thereby activating the n-type latch. The operation of the n-type latch causes the voltage on the bit line /BL to be discharged to ground (OV). After a prescribed period of time, a control signal O2 is driven to a logic "low" level and a control signal O3 is driven to a logic "high" level, thereby turning on the PMOS transistor 30 and activating the p-type latch. The operation of the ptype latch causes the voltage on the bit line BL to rise to the power supply voltage (Vcc)level.
Next, the charge (binary "1" bit of data) read from the selected memory cell 1 is restored (refreshed). More particularly, the row address strobe signal (/RAS) goes "high", the control signal O2 is driven to a logic "high" level, and the control signal O3 is driven to a logic "low" level, thereby turning off the PMOS transistor 30. Next, the control signal O4 is driven to a logic "high" level, thereby causing the voltage Vcc +alpha stored on the NMOS capacitors 33 and 34 to be transferred to the node 41 of the sense amplifier, and subsequently, through the NMOS transistor 28 of the n-type latch and the select or pass transistor 10 of the selected memory cell 1 to the storage capacitor 14 of the selected memory cell 1. Thus, the charge which was originally stored on the storage capacitor 14 and read out onto the bit line BL is restored, or refreshed.
Although the above-described circuit is effective to raise the voltage level of the memory cell to Vcc+ alpha, and thus minimize soft errors, the size of the capacitors 33 and 34 utilized for this purpose occupy valuable real estate on the semiconductor memory chip, thereby constraining the achievable density thereof. The present invention minimizes this shortcoming of the above-described circuit.